Improved inference throughput by 40% and reduced latency by 25% across 15+ biometric pipelines through algorithmic optimizations and parallelization techniques.
Led migration of a point cloud processing platform (Pb/day scale) in C++ to OpenVDB. Reduced build times by 50% for a 50-engineer team via compiler optimizations and automated library installation using Python and Conan.
Rewrote public transport NFC embedded reader (C++) to handle real user behavior, powering Valencia's bus network (77M trips/year).
Improved CPU IPC by 15% by designing a novel L1 Cache (FTC). Achieved 21% energy savings and a 6.4x density increase vs. SRAM, freeing space for accelerators.
With honors on thesis: "Fusion of the L1 and L2 Levels of the Cache Memory Hierarchy Using DWM"
With honors on thesis: "L1 Cache Design using Domain Wall Memory technology"